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NXP Semiconductors /MIMXRT1011 /DCP /CHANNELCTRL_CLR

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Interpret as CHANNELCTRL_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ENABLE_CHANNEL0HIGH_PRIORITY_CHANNEL 0 (CH0_IRQ_MERGED)CH0_IRQ_MERGED

Description

DCP channel control register

Fields

ENABLE_CHANNEL

Setting a bit in this field enables the DMA channel associated with it

1 (CH0): CH0

2 (CH1): CH1

4 (CH2): CH2

8 (CH3): CH3
HIGH_PRIORITY_CHANNEL

Setting a bit in this field causes the corresponding channel to have high-priority arbitration

1 (CH0): CH0

2 (CH1): CH1

4 (CH2): CH2

8 (CH3): CH3
CH0_IRQ_MERGED

Indicates that the interrupt for channel 0 must be merged with the other interrupts on the shared dcp_irq interrupt

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data